1. Field of the Invention
The present invention relates to a read only memory (ROM) device, and more particularly to a read only memory device with a reduced capacitance effect between a numbers of bit lines.
2. Description of the Related Art
U.S. Pat. No. 5,341,337 discloses the circuit architecture of a read only memory device, as shown in FIG. 1. Each of the bit lines Mb is electrically coupled to three bank selection MOSFETs BSO, respectively. The main bit lines, Mb1 to Mb4, can be electrically coupled to a sense amplifier, a ground voltage, or a pre-charge unit. This allows, for example, four continuous main bit lines from left to right to be electrically coupled to the pre-charge units PC1 and PC2, the sense amplifier SA, and the ground voltage terminal, respectively, during the reading of each of the memory cells M. That is, when memory cell M71 is to be read, main bit line Mb1 will be electrically coupled to the pre-charge unit PC1; the main bit line Mb2 will be electrically coupled to the pre-charge unit PC2; the main bit line Mb3 will be electrically coupled to the sense amplifier SA; and the main bit line Mb4 will be electrically coupled to the ground voltage terminal, wherein the pre-charge units PC1 and PC2 and the sense amplifier SA will cause the bit lines Mb to have high voltage.
At this time, the section selection line B02 will be enabled, causing transistors BSO2 and BSO7 to be turned on, thereby sub-bit lines SB3 and SB7 will change to high voltage levels. At the same time, the bank select line BE2 will be turned on, causing transistors BSE2, BSE3, BSE5, and BSE6 to be turned on, and thereby sub-bit line SB4 is converted to a high voltage level and sub-bit line SB8 is changed to the ground voltage. After word line WL1 is turned on, memory cell M71 will be turned on. As a result, the current will flow through sub-bit lines SB7 and SB8. By sensing the amount of current by the sense amplifier SA, the content of memory cell M71 can be read.
However, since transistors BSO4, BSO5, and BSE4 are not turned on, sub-bit lines SB5 and SB6 are floating. The floating sub-bit lines SB5 and SB6 will produce the capacitance effect with sub-bit lines SB4 and SB7, which currently are at a high voltage level. The capacitance effect produced by these floating sub-bit lines will increase the time needed to change the sub-bit line voltage levels. This situation will also cause a reduction in the operating speed for the entire read only memory device. As a result, the conventional read only memory circuit device is not suitable for use at high operating speeds.